In everyday life, the stakes of chip physics show up in small, sharp ways. A video call that suddenly throttles, a lane keeping feature that misbehaves on a wet highway or a factory sensor that drops out in the middle of a run rarely gets blamed on transistor design, yet the root cause often lives there. Underneath those glitches is a supply chain centered on a few advanced fabs and long routes between design, manufacturing and deployment, at the same time that governments are rewriting national security strategies around secure, local access to high end chips. In that context, choices about how transistors, metals and power rails are designed at each node are no longer just engineering tradeoffs; they are part of how a country decides which phones, vehicles and critical systems it can truly rely on.
Sandra Maria Shaji, a design–technology co-optimization (DTCO) engineer at Samsung Semiconductor, works at that junction of physics and design. A judge for the 2025 Globee Awards for Business, she focuses on transistors, wires and power delivery in sub-2-nanometer regimes, connecting device physics to the power, performance and compute density targets that national programs and global customers expect. Her guiding habit is clear: link physics and layout through DTCO so that by the time public money and product roadmaps commit to a node, the hard questions have already been asked.
When Scaling Hits The Limits Of Physics
As advanced nodes carry more of that load, the underlying physics becomes unforgiving for any region that wants dependable, locally produced chips. For leading foundries, technologies at 7 nanometers and below generated more than two thirds of wafer revenue in 2024, and the global advanced-node foundry market reached roughly $28.7 billion that year, and is set to reach $88.5 billion by 2033, as demand rose from premium smartphones, cloud accelerators and automotive controllers. When so much value is concentrated in a few nodes, small misjudgments in power, performance and area can ripple out into delayed phones, postponed vehicle launches or idle factory lines.
Shaji’s early work at Samsung Semiconductor focused on building DTCO flows that make these risks concrete. Drawing on experience from graduate research, where she contributed to a 3-nanometer gate-all-around research PDK, she helped develop an early DTCO infrastructure for a sub 2-nanometer-node technology exploration program. The flow integrated layout processing, LVS, RC extraction and characterization across multiple EDA tools through Python automation, generating design kits and libraries that could support realistic PPA sweeps instead of simple ring oscillators. She remembers one candidate structure that looked compelling at the transistor level but fell behind once interconnect parasitics and realistic routing congestion were modeled; that experiment reinforced her belief that you cannot commit national-scale investments on isolated device metrics.
“From the outside, scaling looks like more performance every generation,” she says. “Inside, it is about discovering which device options survive contact with routing rules, heat and manufacturing limits before anyone pours concrete for a new fab.”
DTCO Infrastructure That De-Risks Public Investment
Those questions take on another dimension when public money and national security are involved. Recent analysis projects that designing a leading-edge 2-nanometer chip could cost around $725 million, while a 2-nanometer-class fabrication plant may require upwards of $30 billion. Under the US CHIPS and Science Act and similar efforts in Europe and Asia, those sums are tied to expectations that new nodes will serve smartphones, cloud and defense platforms, not just a narrow set of designs. If the first generation of a node underdelivers on power or routability, the damage hits more than one product line.
Shaji’s DTCO infrastructure is built to answer that problem directly. Building on publicly documented scaling trends and internally validated process assumptions, she integrated layout processing, parasitic extraction, cell characterization and block-level PPA estimation into a single environment for sub-2-nanometer technology definition. That setup allowed teams to sweep device structures, cell heights, metal stacks and backside power options in a matter of weeks rather than quarters, comparing how each scenario would behave in realistic logic blocks.
“When a government funds a fab or signs a long-term supply deal, it is betting on a node family, not a single tape-out,” she notes. “Our DTCO infrastructure makes sure those families are stress-tested against real PPA and routability constraints before anyone takes that bet.”
Power Delivery, BEOL And Backside Choices For Real Products
Once the basic device stack is credible, wiring and power delivery become the next choke points for local manufacturing plans. Analysts expect worldwide semiconductor manufacturing equipment sales to hit about $125.5 billion in 2025, with semiconductor test equipment alone projected to reach roughly $9.3 billion as new fabs and advanced packaging lines are built. That wave of capex must turn into wiring stacks, backside power grids and power-rail strategies that work for phones, automotive controllers and industrial PCs, not just for a single benchmark design. Routing must still close.
Here Shaji applies DTCO to the back end of the stack. Using a block level PPA estimation method she developed, she has simulated more than a dozen lower metal pitch and spacing combinations to find sweet spots where dynamic power, timing and process cost align with product targets instead of pushing against each other. She has also designed and evaluated performance “booster” standard cells that delivered more than ten percent performance improvement in ultra dense logic regions where conventional ultra high density cells struggled to meet frequency goals. She also co authored an IEEE sponsored conference paper presenting a comparative PPA study of different power-rail architectures in advanced-node standard cells, a line of work that sharpened the way she evaluates power delivery options in her current DTCO role. For design teams working on systems like driver assistance controllers or industrial gateways, those experiments translate into concrete guidance about which BEOL and backside options can support tight power budgets and real time constraints in parts that countries want to manufacture locally.
“Backside power grids and new metal stacks are not academic exercises for us,” she explains. “They are levers we have to get right so that a locally manufactured chip can hit its timing and power numbers in a car, a base station or a factory.”
Preparing For 3D ICs In A World Of Billions Of Devices
Even with better wiring, flat layouts eventually run out of room, especially as compute moves closer to where data is generated. The global 3D IC market reached about $20.2 billion in 2024 and is projected to grow to roughly $96.4 billion by 2033, driven by compact, high-bandwidth electronics. In parallel, the number of active IoT devices worldwide stood at around 17.7 billion in 2024 and is expected to rise to approximately 40.6 billion by 2034, with nodes embedded in vehicles, factories, energy networks and public infrastructure. When that many endpoints depend on dense compute, 3D integration becomes part of national infrastructure planning, not just a technical curiosity.
Shaji has been working toward that future since her time at Georgia Tech. There, she was involved in the development of reinforcement-learning-assisted placement techniques for monolithic 3D ICs and created a full-flow 3-nanometer gate-all-around PDK so researchers could explore stacking and backside-metal schemes when no open advanced-node kits were available. That foundation now shapes how she reads the field’s trajectory. Instead of building stacks, she pays close attention to the signals that indicate which ideas are maturing: peer-reviewed conference results, academic prototypes that push thermal and routing limits, and early explorations of backside networks and tiered architectures. Together, they offer a grounded view of which paths have the structural clarity to scale as national programs plan for denser, higher-bandwidth systems.
“3D stacking is attractive if you only look at bandwidth and density,” she says. “The real work is making sure those stacks can be powered, cooled and routed in a way that fits what phones, cars and factories actually need.”
Looking Ahead, Where Advanced Nodes Serve National Goals
As national strategies converge on secure chip supply, domestic fabs and advanced manufacturing for AI and electrification, the stakes around advanced-node design will keep rising. Recent outlooks indicate that global semiconductor sales could reach about $697 billion in 2025 and keep the industry on track to approach $1 trillion in annual revenue by 2030, with much of the growth coming from AI accelerators, automotive electronics and edge compute. For countries that are putting public capital into fabs and workforce programs, the real question is whether their nodes will support those markets with predictable power, performance and density.
Shaji’s trajectory points directly at that question. At Samsung Semiconductor, she has helped turn early physics and layout exploration into a repeatable DTCO practice that informs technology-definition decisions for future nodes. Outside the company, her role as an editorial board member and reviewer for the International Journal of Artificial Intelligence, Data Science, and Machine Learning (IJAIDSML) keeps her close to new ideas in device modelling and design automation that will shape the next decade of node development. She views all of it through a single lens: how to make early transistor, wiring and packaging choices line up with what local manufacturers, national planners and downstream system designers will actually need.
“Local manufacturing is only one part of the equation,” she notes. “Advancing semiconductor capability depends on how well DTCO and device physics are integrated into that broader effort from the start.”
